1. Technical Field
The embodiments described herein relate to a bit line control circuit of a semiconductor memory apparatus and, more particularly, to a bit line equalizing control circuit of a semiconductor memory apparatus.
2. Related Art
Generally, a semiconductor memory apparatus periodically performs an active operation and a precharge operation. When an active command is input to the semiconductor memory apparatus, a word line is activated, and charge sharing occurs between a bit line and a complement bit line. Accordingly, a bit line sense amplifier is driven so that the voltage of the bit line or the complement bit line is raised to a core voltage level. If a precharge command is input, then the voltage of the bit line and the complement bit line is equalized to a precharge voltage level (one-half of the core voltage level). A time period until a next active command is input to the semiconductor memory apparatus after the precharge command is input is commonly referred to as a row address strobe (RAS) precharge time (tRP). In order to manufacture high-speed memory apparatuses, reduction of the RAS precharge time, which is one of many asynchronous parameters of the memory apparatuses, is important.
FIG. 1 is a schematic block diagram of a conventional bit line equalizing circuit. In FIG. 1, a bit line equalizing circuit 101 includes a first bit line equalization (BLEQ) selecting unit 10(A), a second bit line equalization selecting unit 10(B), and a bit line equalizing driver 20. The first BLEQ selecting unit 10(A) receives a first mat select address signal ‘Mat_Select_ADD(A)’, a first normal row enable signal ‘NRE(A)’, and a first redundancy fuse output signal ‘RedFuse_out(A)’, and produces an output signal ‘/BLEQON(A)’. The second BLEQ selecting unit 10(B) receives a second mat select address signal ‘Mat_Select_ADD(B)’, a second normal row enable signal ‘NRE(B)’, and a second redundancy fuse output signal ‘RedFuse_out(B)’, and produces an output signal ‘/BLEQON(B)’. The bit line equalizing driver 20 receives the output signals ‘/BLEQON(A)’ and ‘/BLEQON(B)’ of the first and second BLEQ selecting units 10(A) and 10(B), respectively, to generate a bit line equalizing signal ‘BLEQ’. Although not shown, the bit line equalizing signal ‘BLEQ’ is input to a bit line sense amplifier. Here, the first and second BLEQ selecting units 10(A) and 10(B) have the same structure.
FIG. 2 is a schematic circuit diagram of a conventional bit line equalizing selecting unit of FIG. 1. In FIG. 2, the BLEQ selecting unit 10 includes a first NAND gate 11, a first inverter 13, a second NAND gate 12, and a second inverter 14. The first NAND gate 11 receives a mat select address signal ‘Mat_Select_ADD’ and a normal row enable signal ‘NRE’. The first inverter 13 inverts a redundancy fuse output signal ‘RedFuse_out’. The second NAND gate 12 receives outputs of the first NAND gate 11 and the first inverter 13, and the second inverter 14 inverts an output of the second NAND gate 12.
FIG. 3 is a schematic circuit diagram of a conventional bit line equalizing driver of FIG. 1. In FIG. 3, the bit line equalizing driver 20 includes a NAND gate 21, a first inverter 22, and a second inverter 23. The NAND gate 21 receives an output of the BLEQ selecting unit 10 (of FIG. 1). The first inverter 22 receives an output of the NAND gate 21, and the second inverter 23 receives an output of the first inverter 22.
A conventional operational procedure of the bit line equalizing circuit will be described. If an array control block is selected by a row address input with an active command, and a mat inside a core cell is selected through the array control block, then both the mat select address signal ‘Mat_Select_ADD’ and the normal row enable signal ‘NRE’ are enabled at a high level. When a mat of a redundancy circuit is selected in order to replace a defected mat detected in a wafer test, the normal row enable signal ‘NRE’ is not enabled, but the redundancy fuse output signal ‘RedFuse_out’ is enabled. When both the normal row enable signal ‘NRE’ and the redundancy fuse output signal ‘RedFuse_out’ are enabled, an output signal ‘/BLEQON’ of the BLEQ selecting unit 10 is enabled at a low level. The bit line equalizing driver 20 receives the output signal ‘/BLEQON’ enabled at a low level to generate the bit line equalizing signal ‘BLEQ’ used to equalize the bit line and the complement bit line.
As shown in FIG. 1, in a semiconductor memory apparatus employing a scheme in which core cells share a sense amplifier, a signal ‘/BLEQON(A)’ or a signal ‘/BLEQON(B)’ is input to the bit line equalizing driver 20 provided in the array control block, and the bit line equalizing signal ‘BLEQ’ is supplied to the same sense amplifier through the bit line equalizing driver 20. Accordingly, the signal ‘/BLEQON(A)’ is output from the first BLEQ selecting unit 10(A) when a predetermined mat is selected from one adjacent core cell, and the signal ‘/BLEQON(B)’ is output from the second BLEQ selecting unit 10(B) when a predetermined mat is selected from another core cell.
A RAS precharge time (tRP) is determined by subtracting a time (Time B) from a time (Time A). Here, the Time A refers to a time period in which the voltage level of the bit line and the complement bit line of the mat becomes a one-half level (VBLP) of a core voltage after the precharge command is input. Similarly, the Time B refers to a time period in which the level of the bit line and the complement bit line is raised to the level of the core voltage after the active command is input. In order to enhance the tRP, the Time A to equalize the bit line and the complement bit line after the precharge command is input must be set within a short period of time, or the Time B to release equalizing of the bit line and the complement bit line after the active command is input must be delayed.
If the tRP is reduced, a high-speed semiconductor memory apparatus can be manufactured. In order to enhance the tRP, only a scheme to reduce the Time A is commonly used instead of a scheme to delay the Time B.